Specifications : Advanced RISC Architecture. 32 x 8 General Purpose Working Registers. Fully Static Operation. Up to 16 MIPS Throughput at 16 MHz. Advanced RISC Architecture. On-chip 2-cycle Multiplier. High Endurance Non-volatile Memory segments. 16 Kbytes of In-System Self-programmable Flash program memory. 512 Bytes EEPROM. 1 Kbyte Internal SRAM. Write/Erase Cycles: 10,000 Flash/100,000 EEPROM. Optional Boot Code Section with Independent Lock Bits. In-System Programming by On-chip Boot Program. True Read-While-Write Operation. Programming Lock for Software Security. JTAG (IEEE std. 1149.1 Compliant) Interface. Boundary-scan Capabilities According to the JTAG Standard. Extensive On-chip Debug Support. Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface. Peripheral Features. Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes. One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode. Real Time Counter with Separate Oscillator. Four PWM Channels. 8-channel, 10-bit ADC. 8 Single-ended Channels. 7 Differential Channels in TQFP Package Only. 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x. Byte-oriented Two-wire Serial Interface. Programmable Serial USART. Master/Slave SPI Serial Interface. Programmable Watchdog Timer with Separate On-chip Oscillator.